View K4H561638D-TCLB0_479511.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

256Mb
Key Features
* Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Four banks operation * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) * All inputs except data & DM are sampled at the positive going edge of the system clock(CK) * Data I/O transactions on both edges of data strobe * Edge aligned data output, center aligned data input * LDM,UDM/DM for write masking only * Auto & Self refresh * 7.8us refresh interval(8K/64ms refresh) * Maximum burst refresh cycle : 8 * 66pin TSOP II package
DDR SDRAM
ORDERING INFORMATION
Part No. K4H560438D-TC/LB3 K4H560438D-TC/LA2 K4H560438D-TC/LB0 K4H560438D-TC/LA0 K4H560838D-TC/LB3 K4H560838D-TC/LA2 K4H560838D-TC/LB0 K4H560838D-TC/LA0 K4H561638D-TC/LB3 K4H561638D-TC/LA2 K4H561638D-TC/LB0 K4H561638D-TC/LA0 16M x 16 32M x 8 64M x 4 Org. Max Freq. B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) A0(DDR200@CL=2) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) A0(DDR200@CL=2) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) A0(DDR200@CL=2) SSTL2 66pin TSOP II SSTL2 66pin TSOP II SSTL2 66pin TSOP II Interface Package
Operating Frequencies
- B3(DDR333) Speed @CL2 Speed @CL2.5 133MHz 166MHz - A2(DDR266A) 133MHz 133MHz - B0(DDR266B) 100MHz 133MHz - A0(DDR200) 100MHz -
*CL : Cas Latency
-1-
Rev. 0.4 May. 2002
256Mb
Package Pinout & Dimension
DDR SDRAM
16Mb x 16 32Mb x 8 64Mb x 4
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
66 PIN TSOP(II) (400mil x 875mil) (0.65 mm PIN PITCH) Bank Address BA0-BA1 Row Address A0-A12 Auto Precharge A10
57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
MS-024FC
42 41 40 39 38 37 36 35 34
256Mb package Pinout
Organization 64Mx4 32Mx8 16Mx16
Column Address A0-A9, A11 A0-A9 A0-A8
DM is internally loaded to match DQ and DQS identically. Column address configuration
-2-
Rev. 0.4 May. 2002
256Mb
Block Diagram (16Mbit x 4 I/O x 4 Banks)
DDR SDRAM
4
WE DM
I/O Control
CK, CK
Data Input Register Serial to parallel
Bank Select
8
8Mx8 Output Buffer 2-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 8Mx8 8Mx8 8Mx8
8 4
x4
DQi
Address Register
CK, CK
ADD
Column Decoder LRAS LCBR Col. Buffer
Latency & Burst Length Strobe Gen. DLL Data Strobe
Programming Register LCKE LRAS LCBR LWE LCAS LWCBR CK, CK Timing Register
DM
CK, CK
CKE
CS
RAS
CAS
WE
DM
-3-
Rev. 0.4 May. 2002
256Mb
Block Diagram (8Mbit x 8 I/O x 4 Banks)
DDR SDRAM
8
WE DM
I/O Control
CK, CK
Data Input Register Serial to parallel
Bank Select
16
4Mx16 Output Buffer 2-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 4Mx16 4Mx16 4Mx16
16 8
x8
DQi
Address Register
CK, CK
ADD
Column Decoder LRAS LCBR Col. Buffer
Latency & Burst Length Strobe Gen. DLL Data Strobe
Programming Register LCKE LRAS LCBR LWE LCAS LWCBR CK, CK Timing Register
DM
CK, CK
CKE
CS
RAS
CAS
WE
DM
-4-
Rev. 0.4 May. 2002
256Mb
Block Diagram (4Mbit x 16 I/O x 4 Banks)
DDR SDRAM
16
LWE LDM
I/O Control
CK, CK
Data Input Register Serial to parallel
Bank Select
32
2Mx32 Output Buffer 2-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 2Mx32 2Mx32 2Mx32
32 16
x16
DQi
Address Register
ADD
Column Decoder LRAS LCBR Col. Buffer
Latency & Burst Length Strobe Gen. DLL Data Strobe
Programming Register LCKE LRAS LCBR LWE LCAS LWCBR CK, CK Timing Register
LDM
CK, CK
CKE
CS
RAS
CAS
WE
L(U)DM
-5-
Rev. 0.4 May. 2002
256Mb
Input/Output Function Description
SYMBOL
CK, CK
DDR SDRAM
TYPE
Input
DESCRIPTION
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognize an LVCMOS LOW level prior to VREF being stable on power-up. Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Data Input/Output : Data bus Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. No Connect : No internal electrical connection is present. DQ Power Supply : +2.5V 0.2V. DQ Ground. Power Supply : +2.5V 0.2V (device specific). Ground. SSTL_2 reference voltage.
CKE
Input
CS
Input
RAS, CAS, WE LDM,(U)DM
Input Input
BA0, BA1 A [n : 0]
Input Input
DQ LDQS,(U)DQS
I/O I/O
NC VDDQ VSSQ VDD VSS VREF
Supply Supply Supply Supply Input
-6-
Rev. 0.4 May. 2002
256Mb
Command Truth Table
COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit
CKEn-1 CKEn CS RAS CAS WE BA0,1
DDR SDRAM
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
A10/AP A11, A12 A9 ~ A0 Note
H H H
X X H L H X X
L L L L H L L
L L L H X L H
L L L H X H L
L L H H X H H V V
OP CODE OP CODE X
1, 2 1, 2 3 3 3 3
L H H
X Row Address L H L H X V X L H X
Column Address
Bank Active & Row Address Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4 4 4, 6 7
H H H
X X X
L L L H L X H L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
V
Column Address
5
Active Power Down
H L H
L H L
X
X
L H H
H
X X H X H X
8 9 9
X
H L
X H
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2.EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
-7-
Rev. 0.4 May. 2002
K4H560438D
16M x 4Bit x 4 Banks Double Data Rate SDRAM
GENERAL DESCRIPTION
DDR SDRAM
The K4H560438D is 268,435,456 bits of double data rate synchronous DRAM organized as 4 x 16,777,216 words by 4 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
Absolute Maximum Rating
Parameter Voltage on any pin relative to VSS Voltage on VDD & VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1.5 50 Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA= 0 to 70C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs Input crossing point voltage, CK and CK inputs Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
Symbol
VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) II IOZ IOH IOL IOH IOL
Min
2.3 2.3 VDDQ/2-50mV VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 1.15 -2 -5 -16.8 16.8 -9 9
Max
2.7 2.7 VDDQ/2+50mV VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.35 2 5
Unit
Note
V V V V V V V V uA uA mA mA mA mA 3 5 1 2 4 4
-8-
Rev. 0.4 May. 2002
K4H560438D
DDR SDRAM
Notes 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
DDR SDRAM IDD spec table
64Mx4 Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A K4H560438D-TC/LB3 (DDR333) 90 110 3 25 20 35 55 150 160 180 3 1.5 290 K4H560438D-TC/LA2, B0 (DDR266A/B) 80 100 3 20 18 30 45 120 135 165 3 1.5 250
(VDD=2.7V, T = 10C)
K4H560438D-TC/LA0 (DDR200) 75 90 3 18 16 25 40 100 110 150 3 1.5 220
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
Optional
AC Operating Conditions
Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 Max Unit V V V V Note 3 3 1 2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Overshoot/Undershoot specification
Specification Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to Address & Control pins 1.6 V 1.6 V 4.5 V-ns 4.5 V-ns Data pins 1.2V 1.2V 2.5 V-ns 2.5 V-ns
-9-
Rev. 0.4 May. 2002
K4H560438D
AC Timming Parameters & Specifications
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup time(slow) Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate Matching Ratio(rise to fall) CL=2.0 CL=2.5
DDR SDRAM
Symbol
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR
-TC/LB3 (DDR333) Min
60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 -0.7 -0.7 0.5 0.5 1.0 0.67 4.5 1.5 +0.7 +0.7 1.1 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 70K
-TC/LA2 (DDR266A) Min
65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
-TC/LB0 (DDR266B) Min
65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
-TC/LA0 (DDR200) Min
70 80 48 20 20 15 15 1 1 10 12 120K
Unit Note
ns ns ns ns ns ns ns tCK tCK ns ns 5 5
Max
Max
Max
Max
0.45 0.45 -0.8 -0.8 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 1.1 1.1 1.1 1.1 -0.8 -0.8 0.5 0.5 1.0 0.67
0.55 0.55 +0.8 +0.8 0.6 1.1 0.6 1.25
tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK 2 5
1.1
tCK ns ns ns ns 6 6 6 6
+0.8 +0.8
ns ns V/ns V/ns 6 7 10
4.5 1.5
V/ns
- 10 -
Rev. 0.4 May. 2002
K4H560438D
-TC/LB3 (DDR333) Min
Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP 0.4 18 (tWR/tCK) + (tRP/tCK) 12 0.45 0.45 2.2 1.75 6 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.55 0.6 0.4 20 (tWR/tCK) + (tRP/tCK)
DDR SDRAM
-TC/LA2 (DDR266A) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.75 0.6 0.4 20 (tWR/tCK) + (tRP/tCK)
Parameter
Symbol
-TC/LB0 (DDR266B) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.75 0.6
-TC/LA0 (DDR200) Min
16 0.6 0.6 2.5 2 10 80 200 7.8 tHP -tQHS tCLmin or tCHmin 0.8 0.4 20 (tWR/tCK) + (tRP/tCK) 0.6
Unit Note
ns ns ns ns ns ns ns tCK us ns ns ns tCK 3 1 5 4 7,8,9 7,8,9
Max
Max
Max
Max
tDAL
tCK
11
1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tIS (ps) 0 +50 +100 tIH (ps) 0 +50 +100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tDS (ps) 0 +75 +150 tDH (ps) 0 +75 +150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate.
- 11 -
Rev. 0.4 May. 2002
K4H560438D
8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 tDS (ps) +50 tDH (ps) +50
DDR SDRAM
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 0.25 0.5 tDS (ps) 0 +50 +100 tDH (ps) 0 +50 +100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.

The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns. CK slew rate (Single ended) 1.0V/ns 0.75V/ns 0.5V/ns tIH/tIS (ps) 0 +50 +100 tDSS/tDSH (ps) 0 +50 +100 tAC/tDQSCK (ps) 0 +50 +100 tLZ(min) (ps) 0 -50 -100 tHZ(max) (ps) 0 +50 +100
- 12 -
Rev. 0.4 May. 2002
K4H560438D
DDR SDRAM
AC Operating Test Conditions
Parameter Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate (for imput only) Input slew rate (I/O pins) Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value
(VDD=2.5V, VDDQ=2.5V, TA= 0 to 70C) Unit V V V/ns V/ns V V V Note
0.5 * VDDQ 1.5 0.5 0.5 VREF+0.31/VREF-0.31 VREF Vtt See Load Circuit
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
(VDD=2.5, VDDQ=2.5V, TA= 25C, f=1MHz) Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Input capacitance( CK, CK ) Data & DQS input/output capacitance Input capacitance(DM) Symbol CIN1 CIN2 COUT CIN3 Min 2 2 4.0 4.0 Max 3.0 3.0 5.0 0.5 5.0 pF Delta Cap(max) 0.5 0.25 Unit pF pF pF
- 13 -
Rev. 0.4 May. 2002
K4H560838D
8M x 8Bit x 4 Banks Double Data Rate SDRAM
GENERAL DESCRIPTION
DDR SDRAM
The K4H560838D is 268,435,456 bits of double data rate synchronous DRAM organized as 4 x 8,388,608 words by 8 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
Absolute Maximum Rating
Parameter Voltage on any pin relative to VSS Voltage on VDD & VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1.5 50 Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA= 0 to 70C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs Input crossing point voltage, CK and CK inputs Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
Symbol
VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) II IOZ IOH IOL IOH IOL
Min
2.3 2.3 VDDQ/2-50mV VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 1.15 -2 -5 -16.8 16.8 -9 9
Max
2.7 2.7 VDDQ/2+50mV VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.35 2 5
Unit
Note
V V V V V V V V uA uA mA mA mA mA 3 5 1 2 4 4
- 14 -
Rev. 0.4 May. 2002
K4H560838D
DDR SDRAM
Notes 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
DDR SDRAM IDD spec table
32Mx8 Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A K4H560838D-TC/LB3 (DDR333) 90 120 3 25 20 35 55 170 170 180 3 1.5 325 K4H560838D-TC/LA2, CB0 (DDR266A/B) 80 110 3 20 18 30 45 140 140 165 3 1.5 280 K4H560838D-TC/LA0 (DDR200) 75 100 3 18 16 25 40 120 115 150 3 1.5 235
(VDD=2.7V, T = 10C)
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
Optional
AC Operating Conditions
Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 Max Unit V V V V Note 3 3 1 2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Overshoot/Undershoot specification
Specification Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to Address & Control pins 1.6 V 1.6 V 4.5 V-ns 4.5 V-ns Data pins 1.2V 1.2V 2.5 V-ns 2.5 V-ns
- 15 -
Rev. 0.4 May. 2002
K4H560838D
AC Timming Parameters & Specifications
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup time(slow) Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate Matching Ratio(rise to fall) CL=2.0 CL=2.5
DDR SDRAM
Symbol
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR
-TC/LB3 (DDR333) Min
60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 -0.7 -0.7 0.5 0.5 1.0 0.67 4.5 1.5 +0.7 +0.7 1.1 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 70K
-TC/LA2 (DDR266A) Min
65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
-TC/LB0 (DDR266B) Min
65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
-TC/LA0 (DDR200) Min
70 80 48 20 20 15 15 1 1 10 12 120K
Unit Note
ns ns ns ns ns ns ns tCK tCK ns ns 5 5
Max
Max
Max
Max
0.45 0.45 -0.8 -0.8 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 1.1 1.1 1.1 1.1 -0.8 -0.8 0.5 0.5 1.0 0.67
0.55 0.55 +0.8 +0.8 0.6 1.1 0.6 1.25
tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK 2 5
1.1
tCK ns ns ns ns 6 6 6 6
+0.8 +0.8
ns ns V/ns V/ns 6 7 10
4.5 1.5
V/ns
- 16 -
Rev. 0.4 May. 2002
K4H560838D
-TC/LB3 (DDR333) Min
Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP 0.4 18 (tWR/tCK) + (tRP/tCK) 12 0.45 0.45 2.2 1.75 6 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.55 0.6 0.4 20 (tWR/tCK) + (tRP/tCK)
DDR SDRAM
-TC/LA2 (DDR266A) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.75 0.6 0.4 20 (tWR/tCK) + (tRP/tCK)
Parameter
Symbol
-TC/LB0 (DDR266B) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.75 0.6
-TC/LA0 (DDR200) Min
16 0.6 0.6 2.5 2 10 80 200 7.8 tHP -tQHS tCLmin or tCHmin 0.8 0.4 20 (tWR/tCK) + (tRP/tCK) 0.6
Unit Note
ns ns ns ns ns ns ns tCK us ns ns ns tCK 3 1 5 4 7,8,9 7,8,9
Max
Max
Max
Max
tDAL
tCK
11
1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tIS (ps) 0 +50 +100 tIH (ps) 0 +50 +100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tDS (ps) 0 +75 +150 tDH (ps) 0 +75 +150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate.
- 17 -
Rev. 0.4 May. 2002
K4H560838D
8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 tDS (ps) +50 tDH (ps) +50
DDR SDRAM
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 0.25 0.5 tDS (ps) 0 +50 +100 tDH (ps) 0 +50 +100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.

The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns. CK slew rate (Single ended) 1.0V/ns 0.75V/ns 0.5V/ns tIH/tIS (ps) 0 +50 +100 tDSS/tDSH (ps) 0 +50 +100 tAC/tDQSCK (ps) 0 +50 +100 tLZ(min) (ps) 0 -50 -100 tHZ(max) (ps) 0 +50 +100
- 18 -
Rev. 0.4 May. 2002
K4H560838D
AC Operating Test Conditions
(VDD=2.5V, VDDQ=2.5V, TA= 0 to 70C) Parameter Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate (for imput only) Input slew rate (I/O pins) Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.5 * VDDQ 1.5 0.5 0.5 VREF+0.31/VREF-0.31 VREF Vtt See Load Circuit
DDR SDRAM
Unit V V V/ns V/ns V V V
Note
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
(VDD=2.5, VDDQ=2.5V, TA= 25C, f=1MHz) Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Input capacitance( CK, CK ) Data & DQS input/output capacitance Input capacitance(DM) Symbol CIN1 CIN2 COUT CIN3 Min 2 2 4.0 4.0 Max 3.0 3.0 5.0 0.5 5.0 pF Delta Cap(max) 0.5 0.25 Unit pF pF pF
- 19 -
Rev. 0.4 May. 2002
K4H561638D
4M x 16Bit x 4 Banks Double Data Rate SDRAM
GENERAL DESCRIPTION
DDR SDRAM
The K4H561638D is 268435456 bits of double data rate synchronous DRAM organized as 4 x 4,194,304 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
Absolute Maximum Rating
Parameter Voltage on any pin relative to VSS Voltage on VDD & VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1.5 50 Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA= 0 to 70C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs Input crossing point voltage, CK and CK inputs Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
Symbol
VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) II IOZ IOH IOL IOH IOL
Min
2.3 2.3 VDDQ/2-50mV VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 1.15 -2 -5 -16.8 16.8 -9 9
Max
2.7 2.7 VDDQ/2+50mV VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.35 2 5
Unit
Note
V V V V V V V V uA uA mA mA mA mA 3 5 1 2 4 4
- 20 -
Rev. 0.4 May. 2002
K4H561638D
DDR SDRAM
Notes 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
DDR SDRAM IDD spec table
16Mx16 Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A K4H561638D-TC/LB3 (DDR333) 90 125 3 25 20 35 55 200 190 180 3 1.5 350 K4H561638D-TC/LA2, B0 (DDR266A/B) 80 115 3 20 18 30 45 170 155 165 3 1.5 300 K4H561638D-TC/LA0 (DDR200) 75 105 3 18 16 25 40 150 130 150 3 1.5 260
(VDD=2.7V, T = 10C)
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
AC Operating Conditions
Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 Max Unit V V V V Note 3 3 1 2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu lation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Overshoot/Undershoot specification
Specification Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to Address & Control pins 1.6 V 1.6 V 4.5 V-ns 4.5 V-ns Data pins 1.2V 1.2V 2.5 V-ns 2.5 V-ns
- 21 -
Rev. 0.4 May. 2002
K4H561638D
AC Timming Parameters & Specifications
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup time(slow) Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate Matching Ratio(rise to fall) CL=2.0 CL=2.5
DDR SDRAM
Symbol
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR
-TC/LB3 (DDR333) Min
60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 -0.7 -0.7 0.5 0.5 1.0 0.67 4.5 1.5 +0.7 +0.7 1.1 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 70K
-TC/LA2 (DDR266A) Min
65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
-TC/LB0 (DDR266B) Min
65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
-TC/LA0 (DDR200) Min
70 80 48 20 20 15 15 1 1 10 12 120K
Unit Note
ns ns ns ns ns ns ns tCK tCK ns ns 5 5
Max
Max
Max
Max
0.45 0.45 -0.8 -0.8 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 1.1 1.1 1.1 1.1 -0.8 -0.8 0.5 0.5 1.0 0.67
0.55 0.55 +0.8 +0.8 0.6 1.1 0.6 1.25
tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK 2 5
1.1
tCK ns ns ns ns 6 6 6 6
+0.8 +0.8
ns ns V/ns V/ns 6 7 10
4.5 1.5
V/ns
- 22 -
Rev. 0.4 May. 2002
K4H561638D
-TC/LB3 (DDR333) Min
Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP 0.4 18 (tWR/tCK) + (tRP/tCK) 12 0.45 0.45 2.2 1.75 6 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.55 0.6 0.4 20 (tWR/tCK) + (tRP/tCK)
DDR SDRAM
-TC/LA2 (DDR266A) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.75 0.6 0.4 20 (tWR/tCK) + (tRP/tCK)
Parameter
Symbol
-TC/LB0 (DDR266B) Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.75 0.6
-TC/LA0 (DDR200) Min
16 0.6 0.6 2.5 2 10 80 200 7.8 tHP -tQHS tCLmin or tCHmin 0.8 0.4 20 (tWR/tCK) + (tRP/tCK) 0.6
Unit Note
ns ns ns ns ns ns ns tCK us ns ns ns tCK 3 1 5 4 7,8,9 7,8,9
Max
Max
Max
Max
tDAL
tCK
11
1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tIS (ps) 0 +50 +100 tIH (ps) 0 +50 +100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tDS (ps) 0 +75 +150 tDH (ps) 0 +75 +150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate.
- 23 -
Rev. 0.4 May. 2002
K4H561638D
8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 tDS (ps) +50 tDH (ps) +50
DDR SDRAM
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 0.25 0.5 tDS (ps) 0 +50 +100 tDH (ps) 0 +50 +100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.

The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns. CK slew rate (Single ended) 1.0V/ns 0.75V/ns 0.5V/ns tIH/tIS (ps) 0 +50 +100 tDSS/tDSH (ps) 0 +50 +100 tAC/tDQSCK (ps) 0 +50 +100 tLZ(min) (ps) 0 -50 -100 tHZ(max) (ps) 0 +50 +100
- 24 -
Rev. 0.4 May. 2002
K4H561638D
AC Operating Test Conditions
(VDD=2.5V, VDDQ=2.5V, TA= 0 to 70C) Parameter Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate (for imput only) Input slew rate (I/O pins) Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.5 * VDDQ 1.5 0.5 0.5 VREF+0.31/VREF-0.31 VREF Vtt See Load Circuit
DDR SDRAM
Unit V V V/ns V/ns V V V
Note
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
(VDD=2.5, VDDQ=2.5V, TA= 25C, f=1MHz) Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Input capacitance( CK, CK ) Data & DQS input/output capacitance Input capacitance(DM) Symbol CIN1 CIN2 COUT CIN3 Min 2 2 4.0 4.0 Max 3.0 3.0 5.0 0.5 5.0 pF Delta Cap(max) 0.5 0.25 Unit pF pF pF
- 25 -
Rev. 0.4 May. 2002

▲Up To Search▲

Price & Availability of K4H561638D-TCLB0

	To Download K4H561638D-TCLB0 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .